The present invention relates to shift registers and, more particularly, to a static shift register capable of implementation by I.sup.2 L techniques.
I.sup.2 L (integrated-injection logic) is a relatively recent development in bipolar semiconductor fabrication techniques, currently being used in the manufacture of large-scale integrated circuits. With this technique, it is possible to merge regions from different transistors in order to increase circuit density and eliminate previously required transistor interconnections. Moreover, the performance characteristics of I.sup.2 L circuits can match, or surpass, those of circuits fabricated by other known techniques. For example, I.sup.2 L circuits are capable of operating faster than N-channel MOS (metal oxide semiconductor) circuits and consuming less power than CMOS (complimentary metal oxide semiconductor) circuits, respectively, the high speed and lower power branches of the MOS family. In the bipolar world, I.sup.2 L offers a meas to maintain higher bipolar speed as circuits reach, and even surpass, LSI complexities previously promissed only by MOS techniques.
The fundamental I.sup.2 L logic unit comprises an inverter transistor and an injector transistor which acts as a current source for the inverter transistor. The inverter transistor physically consists of a vertical NPN multi-emitter bipolar transistor, operated in the inverse mode. In that mode, the conventional bipolar emitters perform as collectors. Base drive to the NPN inverter is supplied by a lateral PNP bipolar transistor, commonly referred to as an injector. On the chip, certain of the diffused areas of the PNP injector are integrated (merged) with those of the PNP inverter in the bulk silicon.
I.sup.2 L can be implemented in conventional bipolar epitaxial technology. As a result, integrated circuit chips employing I.sup.2 L can be fabricated on existing bipolar production lines, thus enabling designers to combine other bipolar technology with I.sup.2 L logic on the same chip.
The high packing density of I.sup.2 L results from the simplicity of its merged structure in the bulk silicon. That simplicity manifests itself in several density enhancing features of the chip layout, including a small number of contacts per gate, complete absence of diffused resistors, no wiring within units, and easy routing of wiring between units.
Other advantages of I.sup.2 L technology include lower source voltage requirements, as compared to MOS technology, immunity to noise and other interference, and the ability to tolerate large power source variations. Moreover, over wide ranges of speed and power dissipation, I.sup.2 L exhibits a near constant power-delay product.
Because of the above-stated advantages of I.sup.2 L technology, it is clear to those skilled in the art that circuits partially or completely fabricated by I.sup.2 L will play a major role in future large-scale integrated circuit fabrication. It is, therefore, necessary for circuit designers to develop basic processing components in I.sup.2 L technology which perform functions similar to the basic processing components utilized in other technologies. However, because of the different properties of I.sup.2 L, new circuit designs are required to take full advantage of the attributes of this technology.
One of the commonly used components in a variety of different processing applications is the shift register. A shift register is basically a device which stores data for a given number of time periods, usually represented by clock pulses. The register receives data signals in time sequence at its input. The data signals are retained by shifting or transferring same within the register, one shift normally occurring for each time period. After the given number of time periods, the data signals appear in the same time sequence at the output of the shift register.
A shift register is comprised of a number of bits or stages which determine the storage capacity thereof. The data signals are transferred from one bit to the next in response to data transfer control signals, the timing of which determines the speed at which the data is transferred from one bit to the next.
Broadly considered, shift registers can be divided into two categories, dynamic and static. In a dynamic shift register, a charge representative of data is temporarily stored in an element by means of a capacitor, often the inherent capacitance of the control terminal of a transistor. Charge stored in this manner will, however, dissipate in a relatively short time. In a dynamic shift register, in order to retain the data therein, the frequency of the shifting of the data (number of times per unit time data is transferred from one element in the register to the next) must be high enough to transfer the stored charge before same dissipates. Thus, while extremely useful in certain applications, dynamic shift registers have an inherent disadvantage, that is, the shifting frequency must always be greater than a lower limit determined by the rate of stored charge dissipation. If the shifting frequency should fall below this limit, the data stored in the shift register is unretrievably lost.
A static shift register, on the other hand, has no lower limit of shifting frequency and, therefore, will retain data therein even at a shifting frequency of zero. This may be accomplished by interconnecting the transistors which go to make up the shift register in a feedback relation, such that the charge stored by the capacitance of one register element is continuously reinforced by the output of another element, connected in feedback relationship thereto, thus preventing the dissipation of the charge, even at a shifting frequency of zero. An excellent example of a static shift register implemented in MOS technology which uses this technique is disclosed in U.S. Pat. No. 3,683,203, entitled ELECTRONIC SHIFT REGISTER SYSTEM, granted to Kent F. Smith on August 8, 1972.
Although I.sup.2 L technology is beginning to find widespread application, only recently have there been attempts to design shift registers employing I.sup.2 L techniques. Some of these attempts resulted in semidynamic shift registers which rely heavily on process parameters and are therefore difficult and expensive to fabricate. In order to avoid process problems, some designers have attempted to design I.sup.2 L static shift registers by functionally copying almost directly from the structure of known MOS static shift registers, resulting in large D-type static registers which are overly complex and do not fully take advantage of the known attributes of I.sup.2 L technology.
It is, therefore, a prime object of the present invention to provide a static shift register which can be implemented in I.sup.2 L technology.
It is another object of the present invention to provide an I.sup.2 L shift register which is simple, compact, and easy to design and fabricate.
It is another object of the present invention to provide an I.sup.2 L shift register wherein each active element thereof is identical to every other active element, facilitating design and fabrication thereof.
It is another object of the present invention to provide an I.sup.2 L static shift register wherein each active element is of simple design.
It is another object of the present invention to provide an I.sup.2 L static shift register which is bi-directional.
It is another object of the present invention to provide an I.sup.2 L static shift register wherein the direction of data transfer is determined solely by the time sequence or order of the components of the data transfer control signal.
It is another object of the present invention to provide an I.sup.2 L static shift register which functions bi-directionally without the necessity for data transfer direction control lines, required by conventional bi-directional shift registers.
It is another object of the present invention to provide an I.sup.2 L shift register wherein resetting is achieved simply by simultaneously holding all of the components of the control signal in the low or "off" condition and thereafter re-starting the control signal with the components thereof in the normal time sequence.
It is another object of the present invention to provide an I.sup.2 L shift register which does not require reset control lines.
It is another object of the present invention to provide an I.sup.2 L shift register with high density due to the elimination of reset control and data transfer direction control lines, normally required by shift registers having reset and bi-directional capabilities.
It is a further object of the present invention to provide an I.sup.2 L shift register which can be fabricated on conventional bi-polar processing equipment.
In accordance with the present invention, a shift register is provided comprising a bit. The bit comprises a given number of active elements operably connected in sequence. Each active element includes an I.sup.2 L unit, operably cross-coupled to an adjacent unit. Means are provided for generating a control signal having a plurality of components, one of which is operably connected to a different one of the active elements in the bit. Each control signal component comprises at least one pulse which is effective, when present, to energize the element to which same is applied, for the duration of the pulse.
The control signal components are generated in a given time sequence of order. The time sequence or order alone determines the direction of data transfer through the register. Thus, a reversal of the time sequence results in a reversal of the direction of data transfer through the bit. No separate data transfer direction control lines to the active elements are required.
Means are provided for resetting the elements. The resetting means comprises means for temporarily deactuating the control signal generating means for a given time period and, thereafter, restarting the control signal generating means. Thus, when the control signal generating means is temporarily deactuated, the shift register is automatically reset. In this manner, no separate reset control lines to the active elements are required.
A control signal component is required for each I.sup.2 L unit in a bit. Each control signal component comprises a series or train of spaced positive clock pulses. The clock pulses of the control signal components may be nonoverlapping or overlapping, as desired.
Each of the active elements has a data input and a data output. The data input of each element is operably connected to the data output of the previous element. The data output of each element is operably connected to the data input of the previous element. Thus, the data input of each element is operably connected in direct relation to the data output of the previous element and in feedback relation to the output of the subsequent element. Viewed in a different manner, each element is operably cross-coupled with both the previous and subsequent elements. From this cross-coupling technique, the static characteristic of the shift register is derived. Each element comprises a control signal input which is operably connected to the control signal generating means to receive one component of the control signal.
Each element is an I.sup.2 L unit which includes a bipolar inverter transistor and a bipolar injector transistor. The inverter transistor and the injector transistor are operably connected between the control signal input and ground.
The injector transistor is a bipolar transistor having a base terminal, a collector terminal and an emitter terminal. The base terminal of the injector transistor is connected to ground. The emitter terminal is operably connected to the control signal input. The collector terminal is operably connected to the inverter transistor to provide base drive therefor.
The inverter transistor of each unit is a bipolar transistor having a base terminal, first and second collector terminals and an emitter terminal. The base terminal is operably connected to the injector transistor, and, more particularly, to the collector terminal thereof. The collector terminals of the inverter transistor are operably connected to the previous I.sup.2 L unit and subsequent I.sup.2 L unit, respectively. The emitter terminal of the inverter transistor is operably connected to ground.
The base terminal of the inverter transistor is also connected to the data input of the unit. The data input of each unit is connected directly to the data output of the previous unit, without an isolation device interposed therebetween. The elimination of the necessity for an isolation device between units significantly simplifies the structure of the shift register.
Since each unit is identical to every other unit in the register, design, layout and fabrication are simplified and relatively inexpensive. In addition, the elimination of the necessity for isolation devices, data transfer direction control lines and reset control lines reduces the complexity and the size of the bits, thereby permitting a larger number of bits to be fabricated in a given chip area.